The present invention relates to a method of making a MOS transistor and a memory cell on a common semiconductor substrate and the device obtained thereby. The invention has particular utility in manufacturing high-density integration semiconductor memory devices, such as flash electrically erasable programmable read only memories (flash EEPROMS), with a design rule of 0.18 micron and under.
The flash EEPROM is so named because the contents of all of the memory""s array cells can be erased simultaneously at high speed. Flash EEPROMs, unlike floating gate EEPROMs which include a separate select transistor in each cell to provide for individual byte erasure, eliminate the select transistor and provide bulk erasure. As a consequence, flash EEPROM cells can be made much smaller than floating gate EEPROM cells fabricated under the same design rules, thus permitting formation of high density memories having easy erasability and reprogrammability.
Conventional flash EEPROMs typically comprise a floating gate memory cell, which includes a source region, a drain region, and a channel region formed in a semiconductor substrate, usually a silicon wafer, and a floating gate formed above the substrate and located between the channel region and a control gate. Most flash EEPROM cells use a xe2x80x9cdouble-polyxe2x80x9d structure, wherein an upper layer formed of, e.g., polysilicon and termed xe2x80x9cpoly 2xe2x80x9d, forms the control gate and a lower layer of polysilicon, termed xe2x80x9cpoly 1xe2x80x9d, forms the floating gate. The gate oxide layer is typically about 10 nm thick and the interpoly dielectric typically comprises a three layer composite of silicon oxide/silicon nitride/silicon oxide layers (xe2x80x9cONOxe2x80x9d) of total thickness of about 25 nm or less.
In operation, to program the memory cell, typically by Channel Hot Electron (xe2x80x9cCHExe2x80x9d) injection, a high voltage, such as about 10 volts, is applied to the control gate and a moderately high voltage, e.g., about 5 volts, is applied to the drain terminal while the source and substrate terminals are at ground potential. To erase the cell, either a Source Edge Erase (xe2x80x9cSEExe2x80x9d) or a Channel Erase (xe2x80x9cCExe2x80x9d) procedure can be utilized. According to the SEE procedure, a high negative voltage, such as xe2x88x9210 volts, is applied to the control gate and a moderately high voltage, e.g., about 5 volts, is applied to the source terminal while the drain potential floats. According to the CE procedure, a high negative voltage, such as xe2x88x9210 volts, is applied to the control gate and a moderately high voltage, e.g., about 7 volts, is applied to the device body (e.g., a well) while the source and drain potentials float. In either instance, a sufficiently large electric field is developed across the tunnel oxide and electrons can tunnel out from the floating gate either at the source terminal (SEE procedure) or through the channel region (CE procedure).
Flash EEPROM systems conventionally comprise a two-dimensional array of floating gate memory cells such as described above. The array typically includes several strings of floating gate memory transistors, each transistor being coupled to the neighboring transistor in the string by coupling the source of one device to the drain of the neighboring device, thereby forming bit lines. A plurality of word lines, perpendicular to the strings, each connect to the control gate of one memory cell of each string.
A CMOS transistor, referred to as a xe2x80x9crow selectorxe2x80x9d, is employed at one end of each word line to supply program voltage on demand to each of the word lines. The row selecting transistor and other transistors, e.g., for power supply purposes, are formed in the semiconductor wafer substrate concurrent with the formation of the memory cell array and typically employ much of the same processing steps and conditions. In some instances, the transistor, termed a xe2x80x9cpoly 2 periphery transistorxe2x80x9d is formed on a peripheral portion of the semiconductor substrate and utilizes the xe2x80x9cpoly 2xe2x80x9d, or upper polysilicon layer used to form the control gates of the memory array cells.
In order to electrically contact the xe2x80x9cpoly 2xe2x80x9d layer forming the gate electrode of. such peripheral transistors and the control gate electrode of the memory array cells, a layer of a refractory metal, e.g., titanium (Ti) or tungsten (W), is typically formed over the xe2x80x9cpoly 2xe2x80x9d electrode (with or without interposition of adhesion and/or barrier layer(s)) and suitably patterned and annealed. The use of tungsten for forming such contacts is particularly attractive because tungstenxe2x80x94based polysilicon gate electrode contacts can be formed with sub-micron sized dimensions (D. Hisamoto et al., 1995 Symposium on VLSI Technology Digest of Technical Papers, pp 115-116), and with very low sheet resistance (i.e., 1.6-3 xcexa9/xe2x96xa1) when either a titanium nitride (TiN) or tungsten nitride (WNx) interlayer is provided between the tungsten layer and the polysilicon gate electrode layer (D. H. Lee et al., 1995 Symposium on VLSI Technology Digest of Technical Papers, pp 119-120; K. Kasai et al., IEDM 94, pp 497-500). However, a significant problem encountered with the use of tungsten as a gate electrode contact metal in memory array manufacture is oxidation thereof during high temperature (e.g., xcx9c900xc2x0 C.) furnace processing under an oxidizing ambient during MOS transistor and flash memory cell fabrication.
Thus, there exists a need for a process scheme, compatible with existing flash memory semiconductor manufacture, which allows formation of very low sheet resistance tungsten gate electrode contacts of deep submicron dimensions while reducing or eliminating oxidation thereof resulting from subsequent processing
An advantage of the present invention is a method of manufacturing a high-density flash memory array with an improved control gate electrode contact structure.
Another advantage of the present invention is a method of forming a flash memory array including a control gate electrode structure which is resistant to oxidation during high temperature processing in an oxidizing ambient.
Still another advantage of the present invention is a method of simultaneously forming oxidation resistant tungsten-based contacts to the gate electrode of a MOS transistor and the control gate electrode of a memory cell of a flash EEPROM.
A still further advantage of the present invention is a high density integration flash EEPROM semiconductor device having a tungsten-based gate electrode contact structure resistant to oxidation.
Additional advantages and other features of the present invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device, which method comprises:
providing a semiconductor substrate comprising silicon and having a surface;
sequentially forming over the substrate a layer stack comprising:
a gate oxide layer (a) on the substrate surface,
an electrically conductive polysilicon layer (b) on the gate oxide layer,
a barrier material layer (c) on the polysilicon layer,
a tungsten layer (d) on the barrier material layer,
a silicon nitride layer (e) on the tungsten layer; and
a polysilicon cap layer (f) on the silicon nitride layer;
selectively removing portions of layers (a)-(f) of the layer stack to define a pattern therein exposing sidewall surfaces of the layer stack;
forming at least one device region in the semiconductor substrate by implantation into the substrate surface, the layer stack serving as an implantation mask;
forming at least one oxide spacer layer (g) covering the uppermost and the exposed sidewall surfaces of the layer stack;
selectively removing at least a portion of the at least one oxide spacer layer (g) on the uppermost surface of the layer stack;
selectively forming a silicon nitride spacer layer (h) over the exposed surfaces of the at least one oxide spacer layer (g) covering the exposed sidewall surfaces of the layer stack, whereby the tungsten layer (d) is encapsulated by the combination of the silicon nitride layer (e) formed on the upper surface thereof and the silicon nitride spacer layer (h) formed over the at least one oxide spacer layer (g); and
annealing the thus-formed layer stack at an elevated temperature in an oxidizing ambient, whereby the silicon nitride encapsulating layers (e) and (h) prevent oxidation of the tungsten layer (d) during the annealing.
According to another aspect of the present invention, the semiconductor device comprises a transistor, the layer stack is formed on at least a peripheral portion of the substrate surface, the electrically conductive polysilicon layer (b) comprises a gate electrode of the transistor, and the tungsten layer (d) comprises a gate electrode contact.
Another aspect of the present invention comprises, after forming gate oxide layer (a) but prior to forming polysilicon layer (b), the steps of:
forming an electrically conductive polysilicon layer (axe2x80x2) on the gate oxide layer (a); and
forming an interpoly dielectric layer (axe2x80x3) on the polysilicon layer (axe2x80x2);
wherein the method further comprises the step of selectively removing portions of polysilicon layer (axe2x80x2) and interpoly dielectric layer (axe2x80x3) to thereby expose sidewall surfaces thereof in substantial vertical registry with the exposed sidewall surfaces of the layer stack; and
the semiconductor device comprises a flash EEPROM, polysilicon layer (axe2x80x2) comprises a floating gate electrode, polysilicon electrode (b) comprises a control gate electrode, and tungsten layer (d) comprises a low sheet resistance control gate electrode contact.
In embodiments according to the present invention, polysilicon layer (b) corresponds to xe2x80x9cpoly 2xe2x80x9d, polysilicon layer (axe2x80x2) corresponds to xe2x80x9cpoly 1xe2x80x9d, the barrier material layer (c) comprises titanium nitride or tungsten nitride, the interpoly dielectric layer (axe2x80x3) comprises a silicon oxide/silicon nitride/silicon oxide (xe2x80x9cONOxe2x80x9d) composite, and the annealing comprises heating in a furnace in an oxygen containing ambient at a temperature of from about 800xc2x0 C. to about 950xc2x0 C. for from about 30 mins. to about 60 mins.
A still further aspect of the present invention is a semiconductor device comprising:
a semiconductor substrate comprising silicon and having a surface with at least one active device region formed therein or thereon;
a layer stack formed on the substrate surface over the at least one active device region, the layer stack comprising, in sequence:
a gate oxide layer (a) on the substrate,
an electrically conductive polysilicon gate electrode layer (b) on the gate oxide layer,
a titanium nitride or tungsten nitride barrier layer (c) on the polysilicon layer,
a tungsten gate electrode contact layer (d) on the barrier layer,
a silicon nitride layer (e) on the tungsten layer, and
a polysilicon cap layer (f) on the tungsten layer,
the layer stack patterned to expose sidewall surfaces of the layers of the layer stack;
at least one oxide spacer layer (g) covering the exposed sidewall surfaces of the layer stack; and
a silicon nitride spacer layer (h) covering the exposed surfaces of the at least one oxide spacer layer (g), wherein the tungsten layer (d) is encapsulated by the combination of the silicon nitride layer (e) formed on the upper surface thereof and by the silicon nitride spacer layer (h) formed on the at least one oxide spacer layer (g), thereby preventing oxidation of tungsten layer (d) during annealing treatment at an elevated temperature in an oxidizing ambient.
According to an aspect of the present invention, the semiconductor device structure comprises a transistor and the at least one active device region is formed at least at a peripheral portion of the semiconductor substrate.
According to a further aspect of the present invention, the layer stack of the semiconductor device structure further comprises an electrically conductive polysilicon layer (axe2x80x2) (=xe2x80x9cpoly 1xe2x80x9d) on the gate oxide layer (a) and a silicon oxide/silicon nitride/silicon oxide (xe2x80x9cONOxe2x80x9d) composite interpoly dielectric layer (axe2x80x3) on the polysilicon layer (axe2x80x2) and under polysilicon layer (b) (=xe2x80x9cpoly 2xe2x80x9d), polysilicon layer (axe2x80x2) and composite interpoly dielectric layer (axe2x80x3) patterned to expose sidewall surfaces thereof in substantial vertical registry with the sidewall surfaces of the layer stack, wherein the semiconductor device structure comprises a flash-type EEPROM, polysilicon layer (axe2x80x2) comprises a floating gate electrode, polysilicon layer (b) comprises a control gate electrode, and tungsten layer (d) comprises a control gate electrode contact.
Additional advantages of the present invention will become readily apparent to those skilled in the art from the following detailed description, wherein only the preferred embodiment of the present invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the method of the present invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawing and description are to be regarded as illustrative in nature, and not as limitative.